Single branch specified, using that and the previous one:
   remotes/brancher/net-next-2025-06-29--21-00 (v6.16-rc3-1062-gd71f4588bcf8)
   remotes/brancher/net-next-2025-06-30--00-00 (v6.16-rc3-1080-ga73d51e7ae1c)

==== BASE IDENTICAL ====
==== COMMIT DIFF ====
diff --git a/tmp/tmp.V5Y2LqXXax b/tmp/tmp.wwfrJGQrfR
index 903e2ba0a1ca..a003c413c179 100644
--- a/tmp/tmp.V5Y2LqXXax
+++ b/tmp/tmp.wwfrJGQrfR
@@ -8,6 +8,24 @@ tc_action dbg [local patch]
 forwarding: set timeout to 3 hours [local patch]
 selftests: net: enable profiling [local patch]
 timestamp - try waking [local patch]
+net: ethernet: mtk_eth_soc: use genpool allocator for SRAM
+net: ethernet: mtk_eth_soc: fix kernel-doc comment
+net: ethernet: mtk_eth_soc: improve support for named interrupts
+net: dsa: hellcreek: Constify struct devlink_region_ops and struct hellcreek_fdb_entry
+dpll: zl3073x: Add support to get/set frequency on output pins
+dpll: zl3073x: Add support to get/set frequency on input pins
+dpll: zl3073x: Implement input pin state setting in automatic mode
+dpll: zl3073x: Add support to get/set priority on input pins
+dpll: zl3073x: Implement input pin selection in manual mode
+dpll: zl3073x: Register DPLL devices and pins
+dpll: zl3073x: Read DPLL types and pin properties from system firmware
+dpll: zl3073x: Add clock_id field
+dpll: zl3073x: Fetch invariants during probe
+dpll: zl3073x: Protect operations requiring multiple register accesses
+dpll: zl3073x: Add support for devlink device info
+dpll: Add basic Microchip ZL3073x support
+dt-bindings: dpll: Add support for Microchip Azurite chip family
+dt-bindings: dpll: Add DPLL device and pin
 selftests: seg6: fix instaces typo in comments
 seg6: fix lenghts typo in a comment
 syztest