WARNING: line length of 82 exceeds 80 columns
#39: FILE: drivers/net/ethernet/xilinx/xilinx_axienet.h:129:
+/* Default TX/RX Threshold and delay timer values for SGDMA mode with DMAEngine */

WARNING: line length of 87 exceeds 80 columns
#118: FILE: drivers/net/ethernet/xilinx/xilinx_axienet_main.c:2277:
+			NL_SET_ERR_MSG(extack, "failed to set tx coalesce parameters");

WARNING: line length of 87 exceeds 80 columns
#124: FILE: drivers/net/ethernet/xilinx/xilinx_axienet_main.c:2283:
+			NL_SET_ERR_MSG(extack, "failed to set rx coalesce parameters");

total: 0 errors, 3 warnings, 0 checks, 89 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit d1562b88edb3 ("net: xilinx: axienet: Configure and report coalesce parameters in DMAengine flow") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT BAD_REPORTED_BY_LINK CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 3 warnings, 0 checks, 89 lines checked