WARNING: line length of 86 exceeds 80 columns
#117: FILE: drivers/net/phy/mxl-86110.c:26:
+#define MXL86110_EXT_SYNCE_CFG_REG						0xA012

WARNING: line length of 99 exceeds 80 columns
#126: FILE: drivers/net/phy/mxl-86110.c:35:
+#define MXL86110_WOL_MAC_ADDR_HIGH_EXTD_REG		0xA007 /* high-> FF:FF                   */

WARNING: line length of 91 exceeds 80 columns
#127: FILE: drivers/net/phy/mxl-86110.c:36:
+#define MXL86110_WOL_MAC_ADDR_MIDDLE_EXTD_REG	0xA008 /*    middle-> :FF:FF <-middle    */

WARNING: line length of 99 exceeds 80 columns
#128: FILE: drivers/net/phy/mxl-86110.c:37:
+#define MXL86110_WOL_MAC_ADDR_LOW_EXTD_REG		0xA009 /*                   :FF:FF <-low */

WARNING: line length of 94 exceeds 80 columns
#136: FILE: drivers/net/phy/mxl-86110.c:45:
+#define MXL86110_EXT_RGMII_CFG1_REG							0xA003

WARNING: line length of 83 exceeds 80 columns
#138: FILE: drivers/net/phy/mxl-86110.c:47:
+#define MXL86110_EXT_RGMII_CFG1_RX_NO_DELAY				(0x0 << 10)

WARNING: line length of 83 exceeds 80 columns
#140: FILE: drivers/net/phy/mxl-86110.c:49:
+#define MXL86110_EXT_RGMII_CFG1_RX_DELAY_1950PS				(0xD << 10)

WARNING: line length of 87 exceeds 80 columns
#141: FILE: drivers/net/phy/mxl-86110.c:50:
+#define MXL86110_EXT_RGMII_CFG1_RX_DELAY_MASK				GENMASK(13, 10)

WARNING: line length of 82 exceeds 80 columns
#143: FILE: drivers/net/phy/mxl-86110.c:52:
+#define MXL86110_EXT_RGMII_CFG1_TX_1G_DELAY_1950PS			(0xD << 0)

WARNING: line length of 85 exceeds 80 columns
#144: FILE: drivers/net/phy/mxl-86110.c:53:
+#define MXL86110_EXT_RGMII_CFG1_TX_1G_DELAY_MASK			GENMASK(3, 0)

WARNING: line length of 82 exceeds 80 columns
#146: FILE: drivers/net/phy/mxl-86110.c:55:
+#define MXL86110_EXT_RGMII_CFG1_TX_10MB_100MB_DELAY_1950PS		(0xD << 4)

WARNING: line length of 95 exceeds 80 columns
#174: FILE: drivers/net/phy/mxl-86110.c:83:
+#define MXL86110_LEDX_CFG_LINK_UP_TX_ACT_ON			BIT(10)	/* LED 0,1,2 default */

WARNING: line length of 95 exceeds 80 columns
#175: FILE: drivers/net/phy/mxl-86110.c:84:
+#define MXL86110_LEDX_CFG_LINK_UP_RX_ACT_ON			BIT(9)	/* LED 0,1,2 default */

WARNING: line length of 90 exceeds 80 columns
#178: FILE: drivers/net/phy/mxl-86110.c:87:
+#define MXL86110_LEDX_CFG_LINK_UP_1GB_ON			BIT(6) /* LED 2 default */

WARNING: line length of 90 exceeds 80 columns
#179: FILE: drivers/net/phy/mxl-86110.c:88:
+#define MXL86110_LEDX_CFG_LINK_UP_100MB_ON			BIT(5) /* LED 1 default */

WARNING: line length of 90 exceeds 80 columns
#180: FILE: drivers/net/phy/mxl-86110.c:89:
+#define MXL86110_LEDX_CFG_LINK_UP_10MB_ON			BIT(4) /* LED 0 default */

WARNING: line length of 86 exceeds 80 columns
#186: FILE: drivers/net/phy/mxl-86110.c:95:
+#define MXL86110_LED_BLINK_CFG_REG						0xA00F

WARNING: line length of 81 exceeds 80 columns
#190: FILE: drivers/net/phy/mxl-86110.c:99:
+#define MXL86110_LED_BLINK_CFG_FREQ_MODE1_16HZ			(BIT(1) | BIT(0))

WARNING: line length of 81 exceeds 80 columns
#194: FILE: drivers/net/phy/mxl-86110.c:103:
+#define MXL86110_LED_BLINK_CFG_FREQ_MODE2_16HZ			(BIT(3) | BIT(2))

WARNING: line length of 82 exceeds 80 columns
#202: FILE: drivers/net/phy/mxl-86110.c:111:
+#define MXL86110_LED_BLINK_CFG_DUTY_CYCLE_17_PERC_ON	(BIT(6) | BIT(5) | BIT(4))

WARNING: line length of 86 exceeds 80 columns
#220: FILE: drivers/net/phy/mxl-86110.c:129:
+static int mxl86110_write_extended_reg(struct phy_device *phydev, u16 regnum, u16 val)

WARNING: line length of 88 exceeds 80 columns
#268: FILE: drivers/net/phy/mxl-86110.c:177:
+static int mxl86110_modify_extended_reg(struct phy_device *phydev, u16 regnum, u16 mask,

WARNING: line length of 84 exceeds 80 columns
#285: FILE: drivers/net/phy/mxl-86110.c:194:
+static void mxl86110_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)

WARNING: line length of 83 exceeds 80 columns
#306: FILE: drivers/net/phy/mxl-86110.c:215:
+static int mxl86110_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)

WARNING: line length of 94 exceeds 80 columns
#323: FILE: drivers/net/phy/mxl-86110.c:232:
+		ret = mxl86110_write_extended_reg(phydev, MXL86110_WOL_MAC_ADDR_HIGH_EXTD_REG,

WARNING: line length of 96 exceeds 80 columns
#328: FILE: drivers/net/phy/mxl-86110.c:237:
+		ret = mxl86110_write_extended_reg(phydev, MXL86110_WOL_MAC_ADDR_MIDDLE_EXTD_REG,

WARNING: line length of 93 exceeds 80 columns
#333: FILE: drivers/net/phy/mxl-86110.c:242:
+		ret = mxl86110_write_extended_reg(phydev, MXL86110_WOL_MAC_ADDR_LOW_EXTD_REG,

WARNING: line length of 84 exceeds 80 columns
#338: FILE: drivers/net/phy/mxl-86110.c:247:
+		ret = mxl86110_modify_extended_reg(phydev, MXL86110_EXT_WOL_CFG_REG,

WARNING: line length of 82 exceeds 80 columns
#339: FILE: drivers/net/phy/mxl-86110.c:248:
+						   MXL86110_EXT_WOL_CFG_WOLE_MASK,

WARNING: line length of 85 exceeds 80 columns
#340: FILE: drivers/net/phy/mxl-86110.c:249:
+						   MXL86110_EXT_WOL_CFG_WOLE_ENABLE);

WARNING: line length of 85 exceeds 80 columns
#351: FILE: drivers/net/phy/mxl-86110.c:260:
+			   __func__, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);

WARNING: line length of 84 exceeds 80 columns
#354: FILE: drivers/net/phy/mxl-86110.c:263:
+		ret = mxl86110_modify_extended_reg(phydev, MXL86110_EXT_WOL_CFG_REG,

WARNING: line length of 82 exceeds 80 columns
#355: FILE: drivers/net/phy/mxl-86110.c:264:
+						   MXL86110_EXT_WOL_CFG_WOLE_MASK,

WARNING: line length of 86 exceeds 80 columns
#356: FILE: drivers/net/phy/mxl-86110.c:265:
+						   MXL86110_EXT_WOL_CFG_WOLE_DISABLE);

WARNING: line length of 82 exceeds 80 columns
#377: FILE: drivers/net/phy/mxl-86110.c:286:
+						 BIT(TRIGGER_NETDEV_HALF_DUPLEX) |

WARNING: line length of 82 exceeds 80 columns
#378: FILE: drivers/net/phy/mxl-86110.c:287:
+						 BIT(TRIGGER_NETDEV_FULL_DUPLEX) |

WARNING: line length of 86 exceeds 80 columns
#468: FILE: drivers/net/phy/mxl-86110.c:377:
+	ret = mxl86110_write_extended_reg(phydev, MXL86110_LED0_CFG_REG + index, val);

WARNING: line length of 83 exceeds 80 columns
#489: FILE: drivers/net/phy/mxl-86110.c:398:
+	 * Configures the clock output to its default setting as per the datasheet.

WARNING: line length of 84 exceeds 80 columns
#527: FILE: drivers/net/phy/mxl-86110.c:436:
+	ret = mxl86110_write_extended_reg(phydev, MXL86110_EXT_RGMII_MDIO_CFG, val);

WARNING: line length of 82 exceeds 80 columns
#540: FILE: drivers/net/phy/mxl-86110.c:449:
+ * By default, each LED blinks only when it is also in the ON state. This function

WARNING: line length of 87 exceeds 80 columns
#546: FILE: drivers/net/phy/mxl-86110.c:455:
+ * /sys/class/led interface; the functions led_hw_is_supported, led_hw_control_get, and

WARNING: line length of 88 exceeds 80 columns
#557: FILE: drivers/net/phy/mxl-86110.c:466:
+		val = mxl86110_read_extended_reg(phydev, MXL86110_LED0_CFG_REG + index);

WARNING: line length of 94 exceeds 80 columns
#562: FILE: drivers/net/phy/mxl-86110.c:471:
+		ret = mxl86110_write_extended_reg(phydev, MXL86110_LED0_CFG_REG + index, val);

WARNING: line length of 83 exceeds 80 columns
#609: FILE: drivers/net/phy/mxl-86110.c:518:
+					   MXL86110_EXT_RGMII_CFG1_FULL_MASK, val);

WARNING: line length of 83 exceeds 80 columns
#613: FILE: drivers/net/phy/mxl-86110.c:522:
+	/* Configure RXDLY (RGMII Rx Clock Delay) to disable the default additional

WARNING: line length of 82 exceeds 80 columns
#618: FILE: drivers/net/phy/mxl-86110.c:527:
+					   MXL86110_EXT_CHIP_CFG_RXDLY_ENABLE, 0);

total: 0 errors, 46 warnings, 0 checks, 602 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit 2b8db16a5773 ("net: phy: add driver for MaxLinear MxL86110 PHY") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT BAD_REPORTED_BY_LINK CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 46 warnings, 0 checks, 602 lines checked