WARNING: line length of 86 exceeds 80 columns #144: FILE: drivers/net/phy/mxl-8611x.c:53: +#define MXL8611X_EXT_SYNCE_CFG_REG 0xA012 WARNING: line length of 99 exceeds 80 columns #153: FILE: drivers/net/phy/mxl-8611x.c:62: +#define MXL86110_WOL_MAC_ADDR_HIGH_EXTD_REG 0xA007 /* high-> FF:FF */ WARNING: line length of 91 exceeds 80 columns #154: FILE: drivers/net/phy/mxl-8611x.c:63: +#define MXL86110_WOL_MAC_ADDR_MIDDLE_EXTD_REG 0xA008 /* middle-> :FF:FF <-middle */ WARNING: line length of 99 exceeds 80 columns #155: FILE: drivers/net/phy/mxl-8611x.c:64: +#define MXL86110_WOL_MAC_ADDR_LOW_EXTD_REG 0xA009 /* :FF:FF <-low */ WARNING: line length of 94 exceeds 80 columns #163: FILE: drivers/net/phy/mxl-8611x.c:72: +#define MXL8611X_EXT_RGMII_CFG1_REG 0xA003 WARNING: line length of 81 exceeds 80 columns #165: FILE: drivers/net/phy/mxl-8611x.c:74: +#define MXL8611X_EXT_RGMII_CFG1_NO_DELAY 0 WARNING: line length of 83 exceeds 80 columns #166: FILE: drivers/net/phy/mxl-8611x.c:75: +#define MXL8611X_EXT_RGMII_CFG1_RX_DELAY_MAX (0xF << 10) WARNING: line length of 83 exceeds 80 columns #167: FILE: drivers/net/phy/mxl-8611x.c:76: +#define MXL8611X_EXT_RGMII_CFG1_RX_DELAY_MIN (0x1 << 10) WARNING: line length of 83 exceeds 80 columns #168: FILE: drivers/net/phy/mxl-8611x.c:77: +#define MXL8611X_EXT_RGMII_CFG1_RX_DELAY_DEFAULT (0xF << 10) WARNING: line length of 87 exceeds 80 columns #170: FILE: drivers/net/phy/mxl-8611x.c:79: +#define MXL8611X_EXT_RGMII_CFG1_RX_DELAY_MASK GENMASK(13, 10) WARNING: line length of 82 exceeds 80 columns #171: FILE: drivers/net/phy/mxl-8611x.c:80: +#define MXL8611X_EXT_RGMII_CFG1_TX_1G_DELAY_MAX (0xF << 0) WARNING: line length of 82 exceeds 80 columns #172: FILE: drivers/net/phy/mxl-8611x.c:81: +#define MXL8611X_EXT_RGMII_CFG1_TX_1G_DELAY_MIN (0x1 << 0) WARNING: line length of 85 exceeds 80 columns #173: FILE: drivers/net/phy/mxl-8611x.c:82: +#define MXL8611X_EXT_RGMII_CFG1_TX_1G_DELAY_MASK GENMASK(3, 0) WARNING: line length of 82 exceeds 80 columns #174: FILE: drivers/net/phy/mxl-8611x.c:83: +#define MXL8611X_EXT_RGMII_CFG1_TX_1G_DELAY_DEFAULT (0x1 << 0) WARNING: line length of 95 exceeds 80 columns #205: FILE: drivers/net/phy/mxl-8611x.c:114: +#define MXL8611X_LEDX_CFG_LINK_UP_TX_ACT_ON BIT(10) /* LED 0,1,2 default */ WARNING: line length of 95 exceeds 80 columns #206: FILE: drivers/net/phy/mxl-8611x.c:115: +#define MXL8611X_LEDX_CFG_LINK_UP_RX_ACT_ON BIT(9) /* LED 0,1,2 default */ WARNING: line length of 90 exceeds 80 columns #209: FILE: drivers/net/phy/mxl-8611x.c:118: +#define MXL8611X_LEDX_CFG_LINK_UP_1GB_ON BIT(6) /* LED 2 default */ WARNING: line length of 90 exceeds 80 columns #210: FILE: drivers/net/phy/mxl-8611x.c:119: +#define MXL8611X_LEDX_CFG_LINK_UP_100MB_ON BIT(5) /* LED 1 default */ WARNING: line length of 90 exceeds 80 columns #211: FILE: drivers/net/phy/mxl-8611x.c:120: +#define MXL8611X_LEDX_CFG_LINK_UP_10MB_ON BIT(4) /* LED 0 default */ WARNING: line length of 86 exceeds 80 columns #217: FILE: drivers/net/phy/mxl-8611x.c:126: +#define MXL8611X_LED_BLINK_CFG_REG 0xA00F WARNING: line length of 81 exceeds 80 columns #221: FILE: drivers/net/phy/mxl-8611x.c:130: +#define MXL8611X_LED_BLINK_CFG_FREQ_MODE1_16HZ (BIT(1) | BIT(0)) WARNING: line length of 81 exceeds 80 columns #225: FILE: drivers/net/phy/mxl-8611x.c:134: +#define MXL8611X_LED_BLINK_CFG_FREQ_MODE2_16HZ (BIT(3) | BIT(2)) WARNING: line length of 82 exceeds 80 columns #233: FILE: drivers/net/phy/mxl-8611x.c:142: +#define MXL8611X_LED_BLINK_CFG_DUTY_CYCLE_17_PERC_ON (BIT(6) | BIT(5) | BIT(4)) WARNING: line length of 85 exceeds 80 columns #260: FILE: drivers/net/phy/mxl-8611x.c:169: +#define MXL86111_EXT_CHIP_CFG_MODE_SEL_MASK GENMASK(2, 0) WARNING: line length of 82 exceeds 80 columns #288: FILE: drivers/net/phy/mxl-8611x.c:197: +/* Customer specific configuration START */ WARNING: line length of 81 exceeds 80 columns #296: FILE: drivers/net/phy/mxl-8611x.c:205: +#define MXL8611X_CLOCK_DISABLE 0 WARNING: line length of 81 exceeds 80 columns #297: FILE: drivers/net/phy/mxl-8611x.c:206: +#define MXL8611X_CLOCK_FREQ_25M 1 WARNING: line length of 81 exceeds 80 columns #298: FILE: drivers/net/phy/mxl-8611x.c:207: +#define MXL8611X_CLOCK_FREQ_125M 2 WARNING: line length of 81 exceeds 80 columns #299: FILE: drivers/net/phy/mxl-8611x.c:208: +#define MXL8611X_CLOCK_DEFAULT 3 WARNING: line length of 82 exceeds 80 columns #312: FILE: drivers/net/phy/mxl-8611x.c:221: +/* Customer specific configuration END */ WARNING: line length of 84 exceeds 80 columns #325: FILE: drivers/net/phy/mxl-8611x.c:234: +static int mxlphy_write_extended_reg(struct phy_device *phydev, u16 regnum, u16 val) WARNING: line length of 82 exceeds 80 columns #344: FILE: drivers/net/phy/mxl-8611x.c:253: +static int mxlphy_locked_write_extended_reg(struct phy_device *phydev, u16 regnum, WARNING: line length of 81 exceeds 80 columns #384: FILE: drivers/net/phy/mxl-8611x.c:293: +static int mxlphy_locked_read_extended_reg(struct phy_device *phydev, u16 regnum) WARNING: line length of 86 exceeds 80 columns #407: FILE: drivers/net/phy/mxl-8611x.c:316: +static int mxlphy_modify_extended_reg(struct phy_device *phydev, u16 regnum, u16 mask, WARNING: line length of 81 exceeds 80 columns #420: FILE: drivers/net/phy/mxl-8611x.c:329: + * mxlphy_locked_modify_extended_reg() - modify bits of a PHY's extended register WARNING: line length of 83 exceeds 80 columns #430: FILE: drivers/net/phy/mxl-8611x.c:339: +static int mxlphy_locked_modify_extended_reg(struct phy_device *phydev, u16 regnum, WARNING: line length of 82 exceeds 80 columns #447: FILE: drivers/net/phy/mxl-8611x.c:356: +static void mxlphy_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) WARNING: line length of 82 exceeds 80 columns #453: FILE: drivers/net/phy/mxl-8611x.c:362: + value = mxlphy_locked_read_extended_reg(phydev, MXL8611X_EXT_WOL_CFG_REG); WARNING: line length of 81 exceeds 80 columns #466: FILE: drivers/net/phy/mxl-8611x.c:375: +static int mxlphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) WARNING: line length of 81 exceeds 80 columns #482: FILE: drivers/net/phy/mxl-8611x.c:391: + page_to_restore = phy_select_page(phydev, MXL86110_DEFAULT_PAGE); WARNING: line length of 92 exceeds 80 columns #487: FILE: drivers/net/phy/mxl-8611x.c:396: + ret = mxlphy_write_extended_reg(phydev, MXL86110_WOL_MAC_ADDR_HIGH_EXTD_REG, WARNING: line length of 94 exceeds 80 columns #491: FILE: drivers/net/phy/mxl-8611x.c:400: + ret = mxlphy_write_extended_reg(phydev, MXL86110_WOL_MAC_ADDR_MIDDLE_EXTD_REG, WARNING: line length of 91 exceeds 80 columns #495: FILE: drivers/net/phy/mxl-8611x.c:404: + ret = mxlphy_write_extended_reg(phydev, MXL86110_WOL_MAC_ADDR_LOW_EXTD_REG, WARNING: line length of 82 exceeds 80 columns #500: FILE: drivers/net/phy/mxl-8611x.c:409: + ret = mxlphy_modify_extended_reg(phydev, MXL8611X_EXT_WOL_CFG_REG, WARNING: line length of 83 exceeds 80 columns #502: FILE: drivers/net/phy/mxl-8611x.c:411: + MXL8611X_EXT_WOL_CFG_WOLE_ENABLE); WARNING: line length of 86 exceeds 80 columns #512: FILE: drivers/net/phy/mxl-8611x.c:421: + __func__, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); WARNING: line length of 81 exceeds 80 columns #515: FILE: drivers/net/phy/mxl-8611x.c:424: + page_to_restore = phy_select_page(phydev, MXL86110_DEFAULT_PAGE); WARNING: line length of 82 exceeds 80 columns #519: FILE: drivers/net/phy/mxl-8611x.c:428: + ret = mxlphy_modify_extended_reg(phydev, MXL8611X_EXT_WOL_CFG_REG, WARNING: line length of 84 exceeds 80 columns #521: FILE: drivers/net/phy/mxl-8611x.c:430: + MXL8611X_EXT_WOL_CFG_WOLE_DISABLE); WARNING: line length of 88 exceeds 80 columns #580: FILE: drivers/net/phy/mxl-8611x.c:489: + ret = mxlphy_write_extended_reg(phydev, MXL8611X_LED0_CFG_REG + i, val); WARNING: line length of 87 exceeds 80 columns #594: FILE: drivers/net/phy/mxl-8611x.c:503: + * address 0 on the MDIO bus. This feature enables PHY to always respond to MDIO access WARNING: line length of 82 exceeds 80 columns #621: FILE: drivers/net/phy/mxl-8611x.c:530: + ret = mxlphy_write_extended_reg(phydev, MXL8611X_EXT_RGMII_MDIO_CFG, val); WARNING: line length of 83 exceeds 80 columns #650: FILE: drivers/net/phy/mxl-8611x.c:559: + FIELD_PREP(MXL8611X_EXT_SYNCE_CFG_CLK_SRC_SEL_MASK, WARNING: line length of 83 exceeds 80 columns #651: FILE: drivers/net/phy/mxl-8611x.c:560: + MXL8611X_EXT_SYNCE_CFG_CLK_SRC_SEL_25M); WARNING: line length of 83 exceeds 80 columns #659: FILE: drivers/net/phy/mxl-8611x.c:568: + FIELD_PREP(MXL8611X_EXT_SYNCE_CFG_CLK_SRC_SEL_MASK, WARNING: line length of 88 exceeds 80 columns #660: FILE: drivers/net/phy/mxl-8611x.c:569: + MXL8611X_EXT_SYNCE_CFG_CLK_SRC_SEL_125M_PLL); WARNING: line length of 89 exceeds 80 columns #674: FILE: drivers/net/phy/mxl-8611x.c:583: + phydev_info(phydev, "%s, clock cfg mask:%d, value: %d\n", __func__, mask, value); WARNING: line length of 83 exceeds 80 columns #677: FILE: drivers/net/phy/mxl-8611x.c:586: + ret = mxlphy_locked_modify_extended_reg(phydev, MXL8611X_EXT_SYNCE_CFG_REG, WARNING: line length of 81 exceeds 80 columns #725: FILE: drivers/net/phy/mxl-8611x.c:634: + MXL8611X_EXT_RGMII_CFG1_FULL_MASK, val); WARNING: line length of 89 exceeds 80 columns #734: FILE: drivers/net/phy/mxl-8611x.c:643: + ret = mxlphy_modify_extended_reg(phydev, MXL8611x_UTP_EXT_SLEEP_CTRL_REG, WARNING: line length of 94 exceeds 80 columns #735: FILE: drivers/net/phy/mxl-8611x.c:644: + MXL8611x_UTP_EXT_SLEEP_CTRL_EN_SLEEP_SW_MASK, WARNING: line length of 94 exceeds 80 columns #736: FILE: drivers/net/phy/mxl-8611x.c:645: + MXL8611x_UTP_EXT_SLEEP_CTRL_EN_SLEEP_SW_OFF); WARNING: line length of 83 exceeds 80 columns #743: FILE: drivers/net/phy/mxl-8611x.c:652: + ret = mxlphy_modify_extended_reg(phydev, MXL86111_EXT_CHIP_CFG_REG, WARNING: line length of 88 exceeds 80 columns #744: FILE: drivers/net/phy/mxl-8611x.c:653: + MXL86111_EXT_CHIP_CFG_RXDLY_ENABLE, 0); WARNING: line length of 93 exceeds 80 columns #762: FILE: drivers/net/phy/mxl-8611x.c:671: + /* dual_media_advertising used for Dual Media mode (MXL86111_EXT_SMI_SDS_PHY_AUTO) */ WARNING: line length of 82 exceeds 80 columns #787: FILE: drivers/net/phy/mxl-8611x.c:696: + old_page = mxlphy_read_extended_reg(phydev, MXL86111_EXT_SMI_SDS_PHY_REG); WARNING: line length of 99 exceeds 80 columns #791: FILE: drivers/net/phy/mxl-8611x.c:700: + if ((old_page & MXL86111_EXT_SMI_SDS_PHYSPACE_MASK) == MXL86111_EXT_SMI_SDS_PHYFIBER_SPACE) WARNING: line length of 95 exceeds 80 columns #828: FILE: drivers/net/phy/mxl-8611x.c:737: + if ((page & MXL86111_EXT_SMI_SDS_PHYSPACE_MASK) == MXL86111_EXT_SMI_SDS_PHYFIBER_SPACE) WARNING: line length of 91 exceeds 80 columns #833: FILE: drivers/net/phy/mxl-8611x.c:742: + return mxlphy_modify_extended_reg(phydev, MXL86111_EXT_SMI_SDS_PHY_REG, mask, set); WARNING: line length of 86 exceeds 80 columns #837: FILE: drivers/net/phy/mxl-8611x.c:746: + * mxl86111_modify_bmcr_paged - modify bits of the PHY's BMCR register of a given page WARNING: line length of 93 exceeds 80 columns #857: FILE: drivers/net/phy/mxl-8611x.c:766: + page_to_restore = phy_select_page(phydev, page & MXL86111_EXT_SMI_SDS_PHYSPACE_MASK); WARNING: line length of 84 exceeds 80 columns #874: FILE: drivers/net/phy/mxl-8611x.c:783: + return phy_restore_page(phydev, page_to_restore, 0); WARNING: line length of 92 exceeds 80 columns #876: FILE: drivers/net/phy/mxl-8611x.c:785: + phydev_warn(phydev, "%s, BMCR reset not completed until timeout", __func__); WARNING: line length of 84 exceeds 80 columns #902: FILE: drivers/net/phy/mxl-8611x.c:811: + ret = mxl86111_modify_bmcr_paged(phydev, priv->reg_page, mask, set); WARNING: line length of 85 exceeds 80 columns #1031: FILE: drivers/net/phy/mxl-8611x.c:940: + * mxl86111_get_features - select the reg space then call mxl86111_get_features_paged WARNING: line length of 82 exceeds 80 columns #1099: FILE: drivers/net/phy/mxl-8611x.c:1008: + ret = mxlphy_locked_modify_extended_reg(phydev, MXL86111_EXT_CHIP_CFG_REG, WARNING: line length of 84 exceeds 80 columns #1100: FILE: drivers/net/phy/mxl-8611x.c:1009: + MXL86111_EXT_CHIP_CFG_MODE_SEL_MASK, WARNING: line length of 89 exceeds 80 columns #1101: FILE: drivers/net/phy/mxl-8611x.c:1010: + MXL86111_EXT_CHIP_CFG_MODE_UTP_TO_RGMII); WARNING: line length of 82 exceeds 80 columns #1105: FILE: drivers/net/phy/mxl-8611x.c:1014: + ret = mxlphy_locked_modify_extended_reg(phydev, MXL86111_EXT_CHIP_CFG_REG, WARNING: line length of 88 exceeds 80 columns #1106: FILE: drivers/net/phy/mxl-8611x.c:1015: + MXL86111_EXT_CHIP_CFG_SW_RST_N_MODE, 0); WARNING: line length of 89 exceeds 80 columns #1110: FILE: drivers/net/phy/mxl-8611x.c:1019: + chip_config = mxlphy_locked_read_extended_reg(phydev, MXL86111_EXT_CHIP_CFG_REG); WARNING: line length of 84 exceeds 80 columns #1140: FILE: drivers/net/phy/mxl-8611x.c:1049: + MXL86111_EXT_SMI_SDS_PHY_REG, WARNING: line length of 83 exceeds 80 columns #1146: FILE: drivers/net/phy/mxl-8611x.c:1055: + phydev_info(phydev, "%s, pinstrap mode: %d\n", __func__, priv->strap_mode); WARNING: line length of 84 exceeds 80 columns #1148: FILE: drivers/net/phy/mxl-8611x.c:1057: + /* configure syncE / clk output - can be defined in custom config section */ WARNING: line length of 81 exceeds 80 columns #1167: FILE: drivers/net/phy/mxl-8611x.c:1076: +static int mxlphy_check_and_restart_aneg(struct phy_device *phydev, bool restart) WARNING: line length of 87 exceeds 80 columns #1176: FILE: drivers/net/phy/mxl-8611x.c:1085: + /* Advertisement did not change, but aneg maybe was never to begin with WARNING: line length of 84 exceeds 80 columns #1310: FILE: drivers/net/phy/mxl-8611x.c:1219: + /* identical to genphy_setup_master_slave, but phy_read without mdio lock */ WARNING: line length of 94 exceeds 80 columns #1318: FILE: drivers/net/phy/mxl-8611x.c:1227: + /* configures/forces speed/duplex, empty rate selection would result in 10M */ WARNING: line length of 88 exceeds 80 columns #1336: FILE: drivers/net/phy/mxl-8611x.c:1245: + /* At least one valid rate must be advertised in Dual Media mode, since it could WARNING: line length of 90 exceeds 80 columns #1337: FILE: drivers/net/phy/mxl-8611x.c:1246: + * lead to permanent blocking of the UTP path otherwise. The PHY HW is controlling WARNING: line length of 89 exceeds 80 columns #1339: FILE: drivers/net/phy/mxl-8611x.c:1248: + * If mode switches to Fiber reg page when a link partner is connected, while UTP WARNING: line length of 90 exceeds 80 columns #1340: FILE: drivers/net/phy/mxl-8611x.c:1249: + * link is down, it can never switch back to UTP if the link cannot be established WARNING: line length of 90 exceeds 80 columns #1341: FILE: drivers/net/phy/mxl-8611x.c:1250: + * anymore due to invalid configuration. A HW reset would be required to re-enable WARNING: line length of 93 exceeds 80 columns #1342: FILE: drivers/net/phy/mxl-8611x.c:1251: + * UTP mode. Therefore prevent this situation and ignore invalid speed configuration. WARNING: line length of 91 exceeds 80 columns #1343: FILE: drivers/net/phy/mxl-8611x.c:1252: + * Returning a negative return code (e.g. EINVAL) results in stack trace dumps from WARNING: line length of 95 exceeds 80 columns #1348: FILE: drivers/net/phy/mxl-8611x.c:1257: + if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->advertising)) WARNING: line length of 95 exceeds 80 columns #1350: FILE: drivers/net/phy/mxl-8611x.c:1259: + if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->advertising)) WARNING: line length of 96 exceeds 80 columns #1352: FILE: drivers/net/phy/mxl-8611x.c:1261: + if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->advertising)) WARNING: line length of 96 exceeds 80 columns #1354: FILE: drivers/net/phy/mxl-8611x.c:1263: + if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->advertising)) WARNING: line length of 97 exceeds 80 columns #1356: FILE: drivers/net/phy/mxl-8611x.c:1265: + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->advertising)) WARNING: line length of 87 exceeds 80 columns #1402: FILE: drivers/net/phy/mxl-8611x.c:1311: + MXL86111_EXT_MISC_CONFIG_FIB_SPEED_SEL, val); WARNING: line length of 87 exceeds 80 columns #1406: FILE: drivers/net/phy/mxl-8611x.c:1315: + ret = mxlphy_modify_extended_reg(phydev, MXL86111_EXT_SDS_LINK_TIMER_CFG2_REG, WARNING: line length of 90 exceeds 80 columns #1407: FILE: drivers/net/phy/mxl-8611x.c:1316: + MXL86111_EXT_SDS_LINK_TIMER_CFG2_EN_AUTOSEN, 0); WARNING: line length of 82 exceeds 80 columns #1412: FILE: drivers/net/phy/mxl-8611x.c:1321: + MXL86111_EXT_CHIP_CFG_SW_RST_N_MODE, 0); WARNING: line length of 87 exceeds 80 columns #1434: FILE: drivers/net/phy/mxl-8611x.c:1343: + ret = mxlphy_modify_extended_reg(phydev, MXL86111_EXT_SDS_LINK_TIMER_CFG2_REG, WARNING: line length of 90 exceeds 80 columns #1435: FILE: drivers/net/phy/mxl-8611x.c:1344: + 0, MXL86111_EXT_SDS_LINK_TIMER_CFG2_EN_AUTOSEN); WARNING: line length of 82 exceeds 80 columns #1440: FILE: drivers/net/phy/mxl-8611x.c:1349: + MXL86111_EXT_CHIP_CFG_SW_RST_N_MODE, 0); WARNING: line length of 88 exceeds 80 columns #1470: FILE: drivers/net/phy/mxl-8611x.c:1379: + /* identical to genphy_check_and_restart_aneg, but phy_read without mdio lock */ WARNING: line length of 84 exceeds 80 columns #1510: FILE: drivers/net/phy/mxl-8611x.c:1419: + priv->dual_media_advertising, fiber_supported); WARNING: line length of 84 exceeds 80 columns #1512: FILE: drivers/net/phy/mxl-8611x.c:1421: + /* ETHTOOL_LINK_MODE_Autoneg_BIT is also used in UTP mode */ WARNING: line length of 96 exceeds 80 columns #1530: FILE: drivers/net/phy/mxl-8611x.c:1439: + "%s, Dual Media mode: page changed during configuration: " \ WARNING: Avoid unnecessary line continuations #1530: FILE: drivers/net/phy/mxl-8611x.c:1439: + "%s, Dual Media mode: page changed during configuration: " \ WARNING: line length of 81 exceeds 80 columns #1545: FILE: drivers/net/phy/mxl-8611x.c:1454: + * mxl86111_config_aneg() - set reg page and then call mxl86111_config_aneg_paged WARNING: line length of 91 exceeds 80 columns #1561: FILE: drivers/net/phy/mxl-8611x.c:1470: + * phydev->advertising need to be saved at first run, since it contains the WARNING: line length of 87 exceeds 80 columns #1562: FILE: drivers/net/phy/mxl-8611x.c:1471: + * advertising which supported by both mac and mxl86111(utp and fiber). WARNING: line length of 81 exceeds 80 columns #1581: FILE: drivers/net/phy/mxl-8611x.c:1490: + linkmode_copy(phydev->advertising, priv->dual_media_advertising); WARNING: line length of 87 exceeds 80 columns #1587: FILE: drivers/net/phy/mxl-8611x.c:1496: + * mxl86111_aneg_done_paged() - determines the auto negotiation result of a given page. WARNING: line length of 93 exceeds 80 columns #1600: FILE: drivers/net/phy/mxl-8611x.c:1509: + page_to_restore = phy_select_page(phydev, page & MXL86111_EXT_SMI_SDS_PHYSPACE_MASK); WARNING: line length of 85 exceeds 80 columns #1655: FILE: drivers/net/phy/mxl-8611x.c:1564: + page_to_restore = phy_select_page(phydev, MXL86111_EXT_SMI_SDS_PHYUTP_SPACE); WARNING: line length of 85 exceeds 80 columns #1687: FILE: drivers/net/phy/mxl-8611x.c:1596: + ret = mxlphy_modify_extended_reg(phydev, MXL8611X_EXT_RGMII_CFG1_REG, WARNING: line length of 89 exceeds 80 columns #1688: FILE: drivers/net/phy/mxl-8611x.c:1597: + MXL8611X_EXT_RGMII_CFG1_FULL_MASK, val); WARNING: line length of 91 exceeds 80 columns #1694: FILE: drivers/net/phy/mxl-8611x.c:1603: + ret = mxlphy_modify_extended_reg(phydev, MXL86111_EXT_CHIP_CFG_REG, WARNING: line length of 96 exceeds 80 columns #1695: FILE: drivers/net/phy/mxl-8611x.c:1604: + MXL86111_EXT_CHIP_CFG_RXDLY_ENABLE, 0); WARNING: line length of 89 exceeds 80 columns #1704: FILE: drivers/net/phy/mxl-8611x.c:1613: + ret = mxlphy_modify_extended_reg(phydev, MXL8611x_UTP_EXT_SLEEP_CTRL_REG, WARNING: line length of 94 exceeds 80 columns #1705: FILE: drivers/net/phy/mxl-8611x.c:1614: + MXL8611x_UTP_EXT_SLEEP_CTRL_EN_SLEEP_SW_MASK, WARNING: line length of 94 exceeds 80 columns #1706: FILE: drivers/net/phy/mxl-8611x.c:1615: + MXL8611x_UTP_EXT_SLEEP_CTRL_EN_SLEEP_SW_OFF); WARNING: line length of 81 exceeds 80 columns #1784: FILE: drivers/net/phy/mxl-8611x.c:1693: + * @is_utp: false(mxl86111 work in fiber mode) or true(mxl86111 work in utp mode) WARNING: line length of 85 exceeds 80 columns #1790: FILE: drivers/net/phy/mxl-8611x.c:1699: +static int mxl86111_adjust_status(struct phy_device *phydev, int status, bool is_utp) WARNING: line length of 90 exceeds 80 columns #1798: FILE: drivers/net/phy/mxl-8611x.c:1707: + duplex = (status & MXL86111_PHY_STAT_DPX) >> MXL86111_PHY_STAT_DPX_OFFSET; WARNING: line length of 94 exceeds 80 columns #1978: FILE: drivers/net/phy/mxl-8611x.c:1887: + phydev->port = (page == MXL86111_EXT_SMI_SDS_PHYFIBER_SPACE) ? WARNING: line length of 89 exceeds 80 columns #1981: FILE: drivers/net/phy/mxl-8611x.c:1890: + phydev_info(phydev, "%s, link up, media: %s\n", __func__, WARNING: line length of 89 exceeds 80 columns #1982: FILE: drivers/net/phy/mxl-8611x.c:1891: + (phydev->port == PORT_TP) ? "UTP" : "Fiber"); WARNING: line length of 93 exceeds 80 columns #1987: FILE: drivers/net/phy/mxl-8611x.c:1896: + /* PHY HW detected UTP port active in parallel to FIBER port. WARNING: line length of 100 exceeds 80 columns #1988: FILE: drivers/net/phy/mxl-8611x.c:1897: + * Since UTP has priority, the page will be hard switched from FIBER WARNING: line length of 100 exceeds 80 columns #1989: FILE: drivers/net/phy/mxl-8611x.c:1898: + * to UTP. This needs to be detected and FIBER link reported as down WARNING: line length of 99 exceeds 80 columns #1992: FILE: drivers/net/phy/mxl-8611x.c:1901: + __func__, (phydev->port == PORT_TP) ? "UTP" : "Fiber"); WARNING: line length of 87 exceeds 80 columns #1999: FILE: drivers/net/phy/mxl-8611x.c:1908: + priv->reg_page = MXL86111_EXT_SMI_SDS_PHY_AUTO; WARNING: line length of 91 exceeds 80 columns #2008: FILE: drivers/net/phy/mxl-8611x.c:1917: + __func__, (phydev->port == PORT_TP) ? "UTP" : "Fiber"); WARNING: line length of 87 exceeds 80 columns #2010: FILE: drivers/net/phy/mxl-8611x.c:1919: + /* When in MXL86111_MODE_AUTO mode, arbitration will be prepare WARNING: line length of 87 exceeds 80 columns #2047: FILE: drivers/net/phy/mxl-8611x.c:1956: + wol_config = mxlphy_locked_read_extended_reg(phydev, MXL8611X_EXT_WOL_CFG_REG); WARNING: line length of 90 exceeds 80 columns #2056: FILE: drivers/net/phy/mxl-8611x.c:1965: + * and the mode might not 'wake up' anymore later on when the other mode is active WARNING: line length of 87 exceeds 80 columns #2074: FILE: drivers/net/phy/mxl-8611x.c:1983: + wol_config = mxlphy_locked_read_extended_reg(phydev, MXL8611X_EXT_WOL_CFG_REG); total: 0 errors, 142 warnings, 0 checks, 2071 lines checked NOTE: For some of the reported defects, checkpatch may be able to mechanically convert to the typical style using --fix or --fix-inplace. Commit e53b41e5987b ("net: phy: mxl-8611: add support for MaxLinear MxL86110/MxL86111 PHY") has style problems, please review. NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT BAD_REPORTED_BY_LINK CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF NOTE: If any of the errors are false positives, please report them to the maintainer, see CHECKPATCH in MAINTAINERS. total: 0 errors, 142 warnings, 0 checks, 2071 lines checked