diff --git a/home/nipa/nipa_out/960881/ynl/old-code/dpll-user.c b/home/nipa/nipa_out/960881/ynl/new-code/dpll-user.c
index ee316c642984..d2d8cd1213b3 100644
--- a/home/nipa/nipa_out/960881/ynl/old-code/dpll-user.c
+++ b/home/nipa/nipa_out/960881/ynl/new-code/dpll-user.c
@@ -158,6 +158,18 @@ const char *dpll_pin_capabilities_str(enum dpll_pin_capabilities value)
 	return dpll_pin_capabilities_strmap[value];
 }
 
+static const char * const dpll_feature_state_strmap[] = {
+	[0] = "disable",
+	[1] = "enable",
+};
+
+const char *dpll_feature_state_str(enum dpll_feature_state value)
+{
+	if (value < 0 || value >= (int)YNL_ARRAY_SIZE(dpll_feature_state_strmap))
+		return NULL;
+	return dpll_feature_state_strmap[value];
+}
+
 /* Policies */
 const struct ynl_policy_attr dpll_frequency_range_policy[DPLL_A_PIN_MAX + 1] = {
 	[DPLL_A_PIN_FREQUENCY_MIN] = { .name = "frequency-min", .type = YNL_PT_U64, },
@@ -204,6 +216,7 @@ const struct ynl_policy_attr dpll_policy[DPLL_A_MAX + 1] = {
 	[DPLL_A_TYPE] = { .name = "type", .type = YNL_PT_U32, },
 	[DPLL_A_LOCK_STATUS_ERROR] = { .name = "lock-status-error", .type = YNL_PT_U32, },
 	[DPLL_A_CLOCK_QUALITY_LEVEL] = { .name = "clock-quality-level", .type = YNL_PT_U32, },
+	[DPLL_A_PHASE_OFFSET_MONITOR] = { .name = "phase-offset-monitor", .type = YNL_PT_U32, },
 };
 
 const struct ynl_policy_nest dpll_nest = {
@@ -534,6 +547,11 @@ int dpll_device_get_rsp_parse(const struct nlmsghdr *nlh,
 				return YNL_PARSE_CB_ERROR;
 			dst->_present.type = 1;
 			dst->type = ynl_attr_get_u32(attr);
+		} else if (type == DPLL_A_PHASE_OFFSET_MONITOR) {
+			if (ynl_attr_validate(yarg, attr))
+				return YNL_PARSE_CB_ERROR;
+			dst->_present.phase_offset_monitor = 1;
+			dst->phase_offset_monitor = ynl_attr_get_u32(attr);
 		}
 	}
 
@@ -652,6 +670,8 @@ int dpll_device_set(struct ynl_sock *ys, struct dpll_device_set_req *req)
 
 	if (req->_present.id)
 		ynl_attr_put_u32(nlh, DPLL_A_ID, req->id);
+	if (req->_present.phase_offset_monitor)
+		ynl_attr_put_u32(nlh, DPLL_A_PHASE_OFFSET_MONITOR, req->phase_offset_monitor);
 
 	err = ynl_exec(ys, nlh, &yrs);
 	if (err < 0)
diff --git a/home/nipa/nipa_out/960881/ynl/old-code/dpll-user.h b/home/nipa/nipa_out/960881/ynl/new-code/dpll-user.h
index b2eeee23cde6..1ac730ffd5d1 100644
--- a/home/nipa/nipa_out/960881/ynl/old-code/dpll-user.h
+++ b/home/nipa/nipa_out/960881/ynl/new-code/dpll-user.h
@@ -26,6 +26,7 @@ const char *dpll_pin_type_str(enum dpll_pin_type value);
 const char *dpll_pin_direction_str(enum dpll_pin_direction value);
 const char *dpll_pin_state_str(enum dpll_pin_state value);
 const char *dpll_pin_capabilities_str(enum dpll_pin_capabilities value);
+const char *dpll_feature_state_str(enum dpll_feature_state value);
 
 /* Common nested types */
 struct dpll_frequency_range {
@@ -164,6 +165,7 @@ struct dpll_device_get_rsp {
 		__u32 temp:1;
 		__u32 clock_id:1;
 		__u32 type:1;
+		__u32 phase_offset_monitor:1;
 	} _present;
 	struct {
 		__u32 module_name;
@@ -181,6 +183,7 @@ struct dpll_device_get_rsp {
 	__s32 temp;
 	__u64 clock_id;
 	enum dpll_type type;
+	enum dpll_feature_state phase_offset_monitor;
 };
 
 void dpll_device_get_rsp_free(struct dpll_device_get_rsp *rsp);
@@ -218,9 +221,11 @@ void dpll_device_get_ntf_free(struct dpll_device_get_ntf *rsp);
 struct dpll_device_set_req {
 	struct {
 		__u32 id:1;
+		__u32 phase_offset_monitor:1;
 	} _present;
 
 	__u32 id;
+	enum dpll_feature_state phase_offset_monitor;
 };
 
 static inline struct dpll_device_set_req *dpll_device_set_req_alloc(void)
@@ -235,6 +240,13 @@ dpll_device_set_req_set_id(struct dpll_device_set_req *req, __u32 id)
 	req->_present.id = 1;
 	req->id = id;
 }
+static inline void
+dpll_device_set_req_set_phase_offset_monitor(struct dpll_device_set_req *req,
+					     enum dpll_feature_state phase_offset_monitor)
+{
+	req->_present.phase_offset_monitor = 1;
+	req->phase_offset_monitor = phase_offset_monitor;
+}
 
 /*
  * Set attributes for a DPLL device