WARNING: line length of 84 exceeds 80 columns
#63: FILE: drivers/net/ethernet/xilinx/xilinx_axienet_main.c:245:
+		u64 clk_rate = 125000000; /* arbitrary guess if no clock rate set */

total: 0 errors, 1 warnings, 0 checks, 92 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit dd4df51d70e9 ("net: xilinx: axienet: Combine CR calculation") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT BAD_REPORTED_BY_LINK CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 1 warnings, 0 checks, 92 lines checked