diff --git a/home/nipa/nipa_out/1017329/ynl/old-code/dpll-user.c b/home/nipa/nipa_out/1017329/ynl/new-code/dpll-user.c
index e464b446bbab..d84c7eb6e130 100644
--- a/home/nipa/nipa_out/1017329/ynl/old-code/dpll-user.c
+++ b/home/nipa/nipa_out/1017329/ynl/new-code/dpll-user.c
@@ -264,6 +264,7 @@ const struct ynl_policy_attr dpll_pin_policy[DPLL_A_PIN_MAX + 1] = {
 	[DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED] = { .name = "esync-frequency-supported", .type = YNL_PT_NEST, .nest = &dpll_frequency_range_nest, },
 	[DPLL_A_PIN_ESYNC_PULSE] = { .name = "esync-pulse", .type = YNL_PT_U32, },
 	[DPLL_A_PIN_REFERENCE_SYNC] = { .name = "reference-sync", .type = YNL_PT_NEST, .nest = &dpll_reference_sync_nest, },
+	[DPLL_A_PIN_PHASE_ADJUST_GRAN] = { .name = "phase-adjust-gran", .type = YNL_PT_U32, },
 };
 
 const struct ynl_policy_nest dpll_pin_nest = {
@@ -938,6 +939,11 @@ int dpll_pin_get_rsp_parse(const struct nlmsghdr *nlh,
 			n_parent_device++;
 		} else if (type == DPLL_A_PIN_PARENT_PIN) {
 			n_parent_pin++;
+		} else if (type == DPLL_A_PIN_PHASE_ADJUST_GRAN) {
+			if (ynl_attr_validate(yarg, attr))
+				return YNL_PARSE_CB_ERROR;
+			dst->_present.phase_adjust_gran = 1;
+			dst->phase_adjust_gran = ynl_attr_get_u32(attr);
 		} else if (type == DPLL_A_PIN_PHASE_ADJUST_MIN) {
 			if (ynl_attr_validate(yarg, attr))
 				return YNL_PARSE_CB_ERROR;
diff --git a/home/nipa/nipa_out/1017329/ynl/old-code/dpll-user.h b/home/nipa/nipa_out/1017329/ynl/new-code/dpll-user.h
index 1bdac5d95a28..b703e78540df 100644
--- a/home/nipa/nipa_out/1017329/ynl/old-code/dpll-user.h
+++ b/home/nipa/nipa_out/1017329/ynl/new-code/dpll-user.h
@@ -487,6 +487,7 @@ struct dpll_pin_get_rsp {
 		__u32 type:1;
 		__u32 frequency:1;
 		__u32 capabilities:1;
+		__u32 phase_adjust_gran:1;
 		__u32 phase_adjust_min:1;
 		__u32 phase_adjust_max:1;
 		__u32 phase_adjust:1;
@@ -517,6 +518,7 @@ struct dpll_pin_get_rsp {
 	__u32 capabilities;
 	struct dpll_pin_parent_device *parent_device;
 	struct dpll_pin_parent_pin *parent_pin;
+	__u32 phase_adjust_gran;
 	__s32 phase_adjust_min;
 	__s32 phase_adjust_max;
 	__s32 phase_adjust;