diff --git a/home/nipa/nipa_out/1006598/ynl/old-code/dpll-user.c b/home/nipa/nipa_out/1006598/ynl/new-code/dpll-user.c
index a4a81e2ffca2..e464b446bbab 100644
--- a/home/nipa/nipa_out/1006598/ynl/old-code/dpll-user.c
+++ b/home/nipa/nipa_out/1006598/ynl/new-code/dpll-user.c
@@ -227,6 +227,7 @@ const struct ynl_policy_attr dpll_policy[DPLL_A_MAX + 1] = {
 	[DPLL_A_LOCK_STATUS_ERROR] = { .name = "lock-status-error", .type = YNL_PT_U32, },
 	[DPLL_A_CLOCK_QUALITY_LEVEL] = { .name = "clock-quality-level", .type = YNL_PT_U32, },
 	[DPLL_A_PHASE_OFFSET_MONITOR] = { .name = "phase-offset-monitor", .type = YNL_PT_U32, },
+	[DPLL_A_PHASE_OFFSET_AVG_FACTOR] = { .name = "phase-offset-avg-factor", .type = YNL_PT_U32, },
 };
 
 const struct ynl_policy_nest dpll_nest = {
@@ -606,6 +607,11 @@ int dpll_device_get_rsp_parse(const struct nlmsghdr *nlh,
 				return YNL_PARSE_CB_ERROR;
 			dst->_present.phase_offset_monitor = 1;
 			dst->phase_offset_monitor = ynl_attr_get_u32(attr);
+		} else if (type == DPLL_A_PHASE_OFFSET_AVG_FACTOR) {
+			if (ynl_attr_validate(yarg, attr))
+				return YNL_PARSE_CB_ERROR;
+			dst->_present.phase_offset_avg_factor = 1;
+			dst->phase_offset_avg_factor = ynl_attr_get_u32(attr);
 		}
 	}
 
@@ -726,6 +732,8 @@ int dpll_device_set(struct ynl_sock *ys, struct dpll_device_set_req *req)
 		ynl_attr_put_u32(nlh, DPLL_A_ID, req->id);
 	if (req->_present.phase_offset_monitor)
 		ynl_attr_put_u32(nlh, DPLL_A_PHASE_OFFSET_MONITOR, req->phase_offset_monitor);
+	if (req->_present.phase_offset_avg_factor)
+		ynl_attr_put_u32(nlh, DPLL_A_PHASE_OFFSET_AVG_FACTOR, req->phase_offset_avg_factor);
 
 	err = ynl_exec(ys, nlh, &yrs);
 	if (err < 0)
diff --git a/home/nipa/nipa_out/1006598/ynl/old-code/dpll-user.h b/home/nipa/nipa_out/1006598/ynl/new-code/dpll-user.h
index 8cb15085830a..1bdac5d95a28 100644
--- a/home/nipa/nipa_out/1006598/ynl/old-code/dpll-user.h
+++ b/home/nipa/nipa_out/1006598/ynl/new-code/dpll-user.h
@@ -260,6 +260,7 @@ struct dpll_device_get_rsp {
 		__u32 clock_id:1;
 		__u32 type:1;
 		__u32 phase_offset_monitor:1;
+		__u32 phase_offset_avg_factor:1;
 	} _present;
 	struct {
 		__u32 module_name;
@@ -278,6 +279,7 @@ struct dpll_device_get_rsp {
 	__u64 clock_id;
 	enum dpll_type type;
 	enum dpll_feature_state phase_offset_monitor;
+	__u32 phase_offset_avg_factor;
 };
 
 void dpll_device_get_rsp_free(struct dpll_device_get_rsp *rsp);
@@ -316,10 +318,12 @@ struct dpll_device_set_req {
 	struct {
 		__u32 id:1;
 		__u32 phase_offset_monitor:1;
+		__u32 phase_offset_avg_factor:1;
 	} _present;
 
 	__u32 id;
 	enum dpll_feature_state phase_offset_monitor;
+	__u32 phase_offset_avg_factor;
 };
 
 static inline struct dpll_device_set_req *dpll_device_set_req_alloc(void)
@@ -341,6 +345,13 @@ dpll_device_set_req_set_phase_offset_monitor(struct dpll_device_set_req *req,
 	req->_present.phase_offset_monitor = 1;
 	req->phase_offset_monitor = phase_offset_monitor;
 }
+static inline void
+dpll_device_set_req_set_phase_offset_avg_factor(struct dpll_device_set_req *req,
+						__u32 phase_offset_avg_factor)
+{
+	req->_present.phase_offset_avg_factor = 1;
+	req->phase_offset_avg_factor = phase_offset_avg_factor;
+}
 
 /*
  * Set attributes for a DPLL device